The present invention relates to a silicon carbide semiconductor device such as a vertical power MOSFET designed for bulk power, formed in a silicon carbide substrate, and a manufacturing method thereof.
A silicon carbide semiconductor device using a silicon carbide (SiC) crystal has a feature that it is excellent in electrical withstand-voltage characteristic and resists operations at high temperatures as compared with a normal semiconductor device using a silicon (Si) crystal.
This is because as a result that the interatomic interval becomes shorter since the carbon (C) atom is contained, stronger interatomic bonding is obtained and the bandgap becomes larger than double, so that the withstand voltage characteristic is enhanced up to an electric field of more than double and the semiconductor characteristic is kept up to high temperatures.
A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used as a conventional vertical silicon carbide semiconductor device using such a property of silicon carbide includes an N+ semiconductor substrate comprised of silicon carbide, in which an N-type conductive impurity is diffused in a high concentration, an N− semiconductor layer formed on the N+ semiconductor substrate, in which the N-type conductive impurity is diffused in a low concentration, a plurality of p-well regions formed by diffusing a P-type conductive impurity on the front surface side of a cell forming area set to the N− semiconductor layer, source layers formed on the front surface side in the p-well regions, in which the N-type conductive impurity is diffused in a high concentration, an outer peripheral insulating film comprised of silicon oxide (SiO2), thicker than a gate oxide film formed on the N− semiconductor layer in an outer peripheral area surrounding the cell forming area by a CVD (Chemical Vapor Deposition) method, an outer peripheral P-well layer which extends from an outer peripheral portion of the cell forming area to the outer peripheral area and is formed by diffusing the P-type conductive impurity on the front surface side of the N− semiconductor layer, a gate oxide film comprised of silicon oxide, which is formed on the front surface of the N− semiconductor layer in the cell forming area by a thermal oxidation method, a gate electrode layer comprised of polysilicon, which is formed so as to extend from above the gate oxide film to above the outer peripheral insulating film, an interlayer insulating film formed on the gate electrode layer, a source electrode pad and a gate electrode pad formed on the interlayer insulating film, which are connected via contact plugs reaching the source layers and the gate electrode layer through the interlayer insulating film, and a drain electrode formed on the back surface of the N+ semiconductor substrate (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2004-288890 (mainly paragraphs 0014 in the 5th page-0019 in the 6th page, paragraph 0022 in the 7th page, and FIG. 1)).
In this case, a high electric field of a few 100V to a few 10 kV is applied to a silicon carbide material between the source and drain formed in a vertical direction. The turning ON and OFF of the MOSFET is controlled by a voltage of a few 10V applied to the gate electrode layer. At this time, an electric field strength of about 3 MV/cm at maximum is generally applied to the gate oxide film. On the other hand, as a vertical trench gate type MOSFET, there has been known one in which an amorphous layer of silicon carbide is formed at the bottom of each trench provided between source layers, the amorphous layer is subjected to speed-increasing oxidation upon thermal oxidation for forming a gate oxide film thereby to make the gate oxide film at each trench bottom thicker, and the gate oxide film that makes the side face of each trench thinner is formed (refer to, for example, a patent document 2 (Japanese Unexamined Patent Publication No. 2006-228901 (mainly paragraphs 0020-0021 in the 7th page, and FIG. 2)).
There has also been known one in which in order to prevent thinning of a gate oxide film due to a step at the boundary between both a device isolation insulating layer embedded into each trench made or created where the device isolation insulating layer is formed in a silicon substrate by an STI method, and the silicon substrate, ions having speed-increasing oxidation action are implanted in a corner portion between the trench and a front surface of the silicon substrate, and the corner portion is subjected to speed-increasing oxidation when the gate oxide film is formed by a thermal oxidation method, thereby forming the gate oxide film at the corner portion thicker (refer to, for example, a patent document 3 (Japanese Unexamined Patent Publication No. 2000-223562 (mainly paragraphs 0061 in the 6th page-0068 in the 7th page, FIG. 8 and FIG. 9)).
Further, there has been known one in which when gate oxide films different in thickness are formed on a silicon substrate, Argon (Ar) ions are implanted in a front surface of the silicon substrate on the film-thickening side to make amorphization thereof, and the amorphized front surface of the silicon substrate is subjected to speed-increasing oxidation when the gate oxide films are formed by a thermal oxidation method, thereby forming the gate oxide films different in thickness (refer to, for example, a patent document 4 (Japanese Unexamined Patent Publication No. 2000-195968 (mainly paragraphs 0031 in the 4th page-0042 in the 5th page, and FIGS. 1 through 6)).
In the prior art according to the patent document 1, however, the outer peripheral insulating film comprised of silicon oxide, which is thicker than the gate oxide film in thickness, is formed on the N− semiconductor layer in the outer peripheral area that surrounds the cello forming area. The gate oxide film comprised of silicon oxide is formed on the front surface of the N− semiconductor layer in the cell forming area by the thermal oxidation method. The gate electrode layer comprising polysilicon is formed so as to extend from above the gate oxide film to above the outer peripheral insulating film. Therefore, when, as illustrated in a typical view of a conventional vertical silicon carbide MOSFET shown in FIG. 9, a thick outer peripheral insulating film 104 comprised of silicon oxide is formed on an N− semiconductor layer 103 in an outer peripheral area 102 surrounding a cell forming area 101 in a silicon carbide semiconductor device 100, and a gate oxide film 105 comprised of silicon oxide is formed on the front surface of the N− semiconductor layer 103 in the cell forming area 101 surrounded by the outer peripheral insulating film 104 by a thermal oxidation method, the N− semiconductor layer 103 is oxidized and its oxidation proceeds in its thickness direction. Hence, a concave portion 106 having a depth equivalent to about one-half the thickness of the gate oxide film 105 is formed as illustrated in an enlarged view of a portion Z shown in FIG. 10.
A problem arises in that since the outer peripheral insulating film 104 is formed of silicon oxide and an end face 104a or the like of the outer peripheral insulating film 104 is not oxidized, the thickness T of the gate oxide film 105 at the boundary between a gate electrode layer 107 formed so as to extend from above the gate oxide film 105 to above the outer peripheral insulating film 104, and the outer peripheral insulating film 104 at a rise portion of the gate electrode layer 107 becomes a thickness equivalent to about one-half the thickness Tg of the gate oxide film 105, and hence an electric field concentrates on an edge portion of the gate oxide film 105 adjacent to the outer peripheral insulating film 104 at which the gate oxide film 105 is made thin, thereby to cause dielectric breakdown, thus shortening insulation withstand-voltage or breakdown lifetime of the gate oxide film 105 and degrading the reliability of the silicon carbon semiconductor device 100.
Incidentally, since the growth rate of a thermal oxide film is slow in the case of a silicon carbide substrate as compared with a silicon substrate (it is an oxidation rate of a few % to a few 10% of that at the silicon substrate), it is not a common practice to use a LOCOS (Local Oxidation of Silicon) method where a thick insulating film comprised of silicon oxide is formed. When, however, a MOSFET having a configuration similar to the above is formed in a silicon substrate 201 as shown in FIG. 11, each device isolation insulating layer 202 is formed by the LOCOS method. Upon its formation, the tip or leading end of the device isolation insulating layer 202 enters a silicon layer in a cell forming area 203, so that a bird's peak 204 having an approximately triangular sectional shape, which consists of silicon oxide, is formed at a boundary portion. Thus, even though when a gate oxide film 205 is formed by a thermal oxidation method, the front surface of the silicon substrate 201 is oxidized and its oxidation proceeds in its thickness direction, the end of the gate oxide film 205 is formed adjacent to the bird's peak 204, and the thickness of the gate oxide film 205 at the boundary between both a gate electrode layer 207 formed so as to extend over an outer peripheral insulating film 206 formed on the corresponding device isolation insulating layer 202 from above the gate oxide film 205, and an outer peripheral insulating film 206 at a rise portion of the gate electrode layer 207 is not made thinner than the thickness Tg of the gate oxide film 205. Thus, the above-described problem does not occur because the field concentration referred to above is relaxed.